As electronic devices get smaller, the components within these devices must get smaller as well. Because of this, there has been an increased demand for the miniaturization of components and greater packaging density. Integrated Circuit (IC) package density is primarily limited by the area available for die mounting and the height of the package. One way of increasing the density is to stack multiple die vertically in an IC package. Currently, die stacking with flash memory, Static Random Access Memory (SRAM), logic and/or Application Specific Integrated Circuit (ASIC) devices have been introduced for increasing the density of chip integration.
In order to provide high quality multi-chip stacked devices, the devices used for stacking must be either high yield FAB (i.e., memory devices) or known good die (KGD). Certain devices, like ASIC and logic devices, have a lower yield than devices like memory. Thus, these types of devices need to be screened if they are to be used in a multi-chip stacked device. A problem arises in that it is expensive to get a KGD prepared. Wafer component testing and burn-in testing is a very expensive process. However, testing of these types of devices is necessary in order to sort out potentially problematic chips and to prevent any quality and reliability issues.
Presently, if a logic or ASIC device in an assembled stacked die package is rejected after testing, the good semiconductor die coupled to these rejected logic or ASIC devices must be scraped. This is problematic for many end customers due to the cost of scraping the good die.
Therefore, a need existed to provide a device and method to overcome the above problems.